Dynamic tag-check omission: a low power instruction cache architecture exploiting execution footprints

Authors:
Koji Inoue;Vasily Moshnyaga;Kazuaki Murakami
Affiliations:
Dept. of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, Japan;Dept. of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, Japan;Dept. of Informatics, Kyushu University, Fukuoka, Japan
Venue:
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Year:
2002

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Abstract

We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multi-media extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.