Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
A framework for dynamic energy efficiency and temperature management
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Instruction flow-based front-end throttling for power-aware high-performance processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Control-theoretic dynamic frequency and voltage scaling for multimedia workloads
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Microarchitecture-level power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Next Generation PowerPC" Microprocessor Test Strategy Improvements
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Energy efficient co-adaptive instruction fetch and issue
Proceedings of the 30th annual international symposium on Computer architecture
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
A performance-conserving approach for reducing peak power consumption in server systems
Proceedings of the 19th annual international conference on Supercomputing
Optimizing the Thermal Behavior of Subarrayed Data Caches
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Exploring "temperature-aware" design in low-power MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Throttling-Based Resource Management in High Performance Multithreaded Architectures
IEEE Transactions on Computers
Synergistic temperature and energy management in GALS processor architectures
Proceedings of the 2006 international symposium on Low power electronics and design
Dynamic thermal management for MPEG-2 decoding
Proceedings of the 2006 international symposium on Low power electronics and design
Active bank switching for temperature control of the register file in a microprocessor
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Physical aware frequency selection for dynamic thermal management in multi-core systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temperature-aware leakage minimization technique for real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Predictive thermal management for hard real-time tasks
ACM SIGBED Review - Special issue: The work-in-progress (WIP) session of the RTSS 2005
Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Reactive speed control in temperature-constrained real-time systems
Real-Time Systems
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
A framework for predictive dynamic temperature management of microprocessor systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Early-stage definition of LPX: a low power issue-execute processor
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Multi-processor computer system having low power consumption
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Hardware/software co-design architecture for thermal management of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting narrow-width values for thermal-aware register file designs
Proceedings of the Conference on Design, Automation and Test in Europe
Low power microprocessor design for embedded systems
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
Microvisor: a runtime architecture for thermal management in chip multiprocessors
Transactions on High-Performance Embedded Architectures and Compilers IV
Multi-level simultaneous multithreading scheduling to reduce the temperature of register files
Concurrency and Computation: Practice & Experience
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
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Thermal management is an important design issue in high performance, low-power portable computers. ofthe computer system is designed for worst-case processor power dissipation and environmental operating conditions, it will carry an area and cost penalty for the system designer: The next generation PowerPCTM microprocessor includes a Thermal Assist Unit (TAU) comprised of an on-chip thermal sensor and associated logic. The TAU monitors the junction temperature of the processor and dynamically adjusts processor operation to provide maximum performance under changing environmental conditions. The TAU is used in conjunction with other low power features such as dynamic power management, instruction cache throttling, and static low power tnodes to provide comprehensive power and thermal management. This paper will describe the implementation of the TAU and present characterization and operating data from$rst silicon.