Thermal Management System for High Performance PowerPCTM Microprocessors
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Traditional inaccuracies during manufacturing test of the thermal sensor circuit require excessive guard-bands. These guard-bands increase the chance of unnecessary microprocessor throttling and could introduce a less-than optimum power and thermal design envelope. Circuit techniques that minimize these errors are discussed, including an improved temperature-independent voltage pump, a remote thermal sensing scheme for hot-spot to sensor offset reduction, and a self-heating error calibration method. Experimental data obtained on a high performance 65nm Intel® Pentium® 4 microprocessor demonstrates the feasibility and effectiveness of these techniques, providing a combined potential accuracy improvement of up to 17°C.