ACM Transactions on Computer Systems (TOCS)
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Dynamic Power Management for Microprocessors: A Case Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Proceedings of the 2003 international symposium on Low power electronics and design
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Process Variation Tolerant Online Current Monitor for Robust Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Reducing dynamic and leakage energy in VLIW architectures
ACM Transactions on Embedded Computing Systems (TECS)
Compiler-directed thermal management for VLIW functional units
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Proceedings of the 43rd annual Design Automation Conference
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A simple built-in current sensor for IDDQ testing of CMOS data converters
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
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Energy reduction of functional units (FUs) is a very important concern for high-end superscalar processors, not only because FUs consume a significant portion of processor energy, but also because they are one of the most important hotspots in the processor. In addition, the high sensitivity of leakage on temperature and process variation result in very high variation in the FU power consumption in different processor dies. Such high process variation reduces the parametric yield of processors. Consequently, reducing the FU power consumption and its variation is an important problem. However, existing FU power reduction techniques assumes all the FUs are similar, and do not consider the sensitivity of leakage on temperature. Consequently, they are not very effective in reducing the variation of FU power consumption. The advent of extremely small, yet accurate leakage sensors allow us to develop leakage-aware microarchitectural techniques to reduce both the power consumption and its variation among processor dies. Our leakage-aware operation-to-FU binding mechanism (LA-OFBM) and leakage-aware power gating (LA-PG) mechanisms reduce the mean and standard deviation of the total arithmetic logic unit (ALU) power consumption of the ALPHA 21364 by 34% and 59%, respectively. At the processor level, this translates to a 13% reduction in the total processor energy consumption, with a 24 ° C reduction in the maximum ALU temperature.