Variation resilient low-power circuit design methodology using on-chip phase locked loop
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ABRM: adaptive β-ratio modulation for process-tolerant ultradynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive keeper design for dynamic logic circuits using rate sensing technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Proceedings of the International Conference on Computer-Aided Design
Integration, the VLSI Journal
Domino logic designs for high-performance and leakage-tolerant applications
Integration, the VLSI Journal
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This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5× reduction in the number of robustness failing dies, compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. Results based on measured leakage data show 1.9-10.2× higher signal-to-noise ratio (SNR) and reduced sensitivity to supply and p-n skew variations compared to prior leakage sensor designs.