Variation resilient low-power circuit design methodology using on-chip phase locked loop

Authors:
Kunhyuk Kang;Keejong Kim;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
Proceedings of the 44th annual Design Automation Conference
Year:
2007

Citing 6
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Abstract

This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize on-chip phase locked loop (PLL) as a sensor to detect process, VDD, and temperature (PVT) variations or even temporal degradation stemming from negative bias temperature instability (NBTI). We will show that control voltage (Vcnt) of voltage controlled oscillator (VCO) in PLL can dynamically capture performance variations in circuit. By utilizing the Vcnt signal of PLL, we propose variation resilient circuit design using adaptive body bias (VR-ABB). Vcnt is used to generate an optimal body bias for various circuit blocks in order to avoid possible timing failures. Correspondingly, circuits can be designed with a significantly relaxed timing constraint compared to the conventional approaches, where a large amount of design resources can be wasted to take care of the worst case situations. We have demonstrated our approach using an 8 bit Ripple Carry Adder (RCA) as an example circuit. Results show that even under extreme variations, reasonable parametric yield can be maintained while minimizing other design resources such as area and power.