Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variation resilient low-power circuit design methodology using on-chip phase locked loop
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring
Proceedings of the 49th Annual Design Automation Conference
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
On-chip process variations compensation using an analog adaptive body bias (A-ABB)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Journal of Electronic Testing: Theory and Applications
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Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (VDD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (Vcnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLL Vcnt signal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in [1] with major improvements in measurement results and analysis.