Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electrical Modeling of Lithographic Imperfections
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits
IEEE Transactions on Circuits and Systems II: Express Briefs
Dynamic supply and threshold voltage scaling for CMOS digital circuits using in-situ power monitor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ITRS design technology and system drivers roadmap: process and status
Proceedings of the 50th Annual Design Automation Conference
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VLSI circuits usually allocate excess margin to account for worst-case process variation. Since most chips are fabricated at process conditions better than the worst-case corner, adaptive voltage scaling (AVS) is commonly used to reduce power consumption whenever possible. A typical AVS setup relies on a performance monitor that replicates critical paths of the circuit to guide voltage scaling. However, it is difficult to define appropriate critical paths for an SoC which has multiple operating modes and IPs. In this paper, we propose a different methodology for AVS which matches the voltage scaling characteristics of a circuit rather than the delays of critical paths. This fundamental change in monitoring strategy simplifies the monitoring circuitry as well as the calibration flow of conventional monitoring methods. To enable the proposed methodology, we study voltage scaling characteristics of digital circuits. Based on our analyses, we develop design guidelines as well as design monitoring circuits which have tunable voltage scaling characteristics. Our experimental results show that this methodology can be used for AVS with a simplified calibration flow.