ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Data driven signal processing: an approach for energy efficient computing
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
High-efficiency multiple-output DC-DC conversion for low-voltage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Enabling adaptability through elastic clocks
Proceedings of the 46th Annual Design Automation Conference
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software adaptation in quality sensitive applications to deal with hardware variability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Dynamic clock stretching for variation compensation in VLSI circuit design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
AppAdapt: opportunistic application adaptation in presence of hardware variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic supply and threshold voltage scaling for CMOS digital circuits using in-situ power monitor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Conventional voltage scaling Systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-µm technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16 × 16 bit multiplier.