A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The impact of variability on power
Proceedings of the 2004 international symposium on Low power electronics and design
Power Variability and Its Impact on Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A novel approach for variation aware power minimization during gate sizing
Proceedings of the 2006 international symposium on Low power electronics and design
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Variation Aware Timing Based Placement Using Fuzzy Programming
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elastic Timing Scheme for Energy-Efficient and Robust Performance
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Statistical timing analysis of combinational logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the nanometer era, process, voltage, and temperature variations are dominating circuit performance, power, and yield. Over the past few years, statistical optimization methods have been effective in improving yield in the presence of uncertainty due to process variations. However, statistical methods overconsume resources, even in the absence of variations. Hence, to facilitate a better performance-power-yield trade-off, techniques that can dynamically enable variation compensation are becoming necessary. In this article, we propose a dynamic technique that controls the instance of data capture in critical path memory flops, by delaying the clock edge trigger. The methodology employs a dynamic delay detection circuit to identify the uncertainty in delay due to variations and stretches the clock in the destination flip-flops. The delay detection circuit uses a latch and set of combinational gates to dynamically detect and create the slack needed to accommodate the delay due to variations. The Clock Stretching Logic (CSL) is added only to paths, which have a high probability of failure in the presence of variations. The proposed methodology improves the timing yield of the circuit without significant overcompensation. The methodology approach was simulated using Synopsys design tools for circuit synthesis and Cadence tools for placement and routing of the design. Extraction of parasitic of timing information was parsed using Perl scripts and simulated using a simulation program generated in C++. Experimental results based on Monte-Carlo simulations on benchmark circuits indicate considerable improvement in timing yield with negligible area overhead.