Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic clock stretching for variation compensation in VLSI circuit design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The integrated circuit manufacturing process has inevitableimperfections and fluctuations that result in ever-growingsystematic and random variations in the electrical parameters ofactive and passive devices fabricated. The impact of suchvariations on various aspects of chip performance has been thesubject of numerous papers, and techniques for analyzing anddealing with such variability-broadly labelled design formanufacturability are emerging as the next hot topic in thisarea.The focus of much of the current work in this area has been ontiming, but it is well known that modern integrated circuits arevery heavily power limited and that static and dynamic power haveemerged as first class design objectives.In this paper, we review the various sources of processvariability, and relate them to variability in the various parts ofthe power delivery subsystem. Specifically, we address variabilityin the following areas: Static (leakage) power.This is the portion of the power dissipated in the integratedcircuit which exists when the power is applied, but circuits arenot operating. This part of the overall power problem has beenreceiving much attention recently since technology scaling has beencausing a large increase in intrinsic device leakage.Dynamic power. This is the power required to operatedigital switching circuits such as buffers, latches, memory arraysand logic gates. The estimation of dynamic power has been the areaof much research over the last 20 or so years. To a large degree,however, the impact of manufacturing variability in this area hasnot received much attention. On-chip powergrid. This takes into account variability in the integrated circuitwires and vias that constitute the chip power grid. Power gridwires encompass all metal levels (layers) in a design and oftenoccupy 20 percent or more of the total wiring resources. Thedistributed nature of the power grid is intended to decrease itssensitivity to certain types of variation.On-chip decoupling capacitance. This models the impact ofvariability on the various components of on-chip decouplingcapacitance including both special-purpose decoupling capacitors aswell as the so-called quiet capacitanceassociated with circuits which are not switching. This is a subjectwhich has received very little attention, but is becoming crucialfor high speed multi-GHz designs. Packagepower grid. This includes the effect of tolerances and variationsin the manufacture of the package. Since the package ismanufactured using a process distinct from that of integratedcircuit fabrication, the character of the variations isdifferent. Workload. One source of uncertaintyin power delivery is lack of detailed knowledge of designoperation. Some of this lack of detailed knowledge is due to thefact that power delivery systems (both on chip and package) areoften designed concurrently with the design, leading to a lack ofdetailed placement information and power estimates for parts of thedesign. Nevertheless, this source of variability is important andneeds to be considered along with the other morephysical sourcesabove.It is important to model all these sources of variability withthe correct balance of effort and accuracy, thus it is important toget broad bounds on each of the sources in order to insure that theappropriate level of modeling and analysis investment is made inorder to bound or worst-case each component without unduepessimism.It is also important to have a first order understanding of thetechnology trends in each of these sources of variability. Thiswill allow the designer and CAD tool developer to anticipate futureproblem areas and plan work arounds as needed.