Run-time power control scheme using software feedback loop for low-power real-time application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
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A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.