Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Active mode leakage reduction using fine-grained forward body biasing strategy
Proceedings of the 2004 international symposium on Low power electronics and design
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Timing-reasoning-based delay fault diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability analysis under layout pattern-dependent rapid-thermal annealing process
Proceedings of the 46th Annual Design Automation Conference
A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities
ATS '09 Proceedings of the 2009 Asian Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays or tuning down on fast cells to save power. On our test cases, we can correct up to 75% of failed chips to pass performance tests, while maintaining less than 10% increase over nominal power consumption.