ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy attacks and defense techniques for wireless systems
Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip process variations compensation using an analog adaptive body bias (A-ABB)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The economics of continued scaling of silicon process technologies beyond the 90-nm node will face significant challenges due to variability. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus, reducing manufacturing yields. Mitigating the effects of these process variations can be done by using the proposed individual well-adaptive body biasing (IWABB) scheme of locally generated body biases. IWABB allows for highly localized circuit optimizations with very little overhead in silicon area and routing resources. We present two algorithms to find near-optimal configurations of these biases which can be applied as postsilicon tuning. The proposed IWABB scheme can improve an initial yield from 12% to 73%.