A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs

Authors:
Masayuki Miyazaki;Hiroyuki Mizuno;Koichiro Ishibashi
Affiliations:
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185-8601 Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185-8601 Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, 185-8601 Japan
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

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Abstract

In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25-µm CMOS devices as a test circuit, we found that the worst-case operating frequency was improved from 20 MHz to 55 MHz, and the fluctuation of the operating frequency was suppressed from 44 % to 15 % while the supply-voltage variation was under 0.1 V with a 1.8 V supply voltage.