Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
One Digital Day: How the Microchip Is Changing Our World
One Digital Day: How the Microchip Is Changing Our World
MONOLITHIC DC-DC CONVERTER ANALYSIS AND MOSFET GATE VOLTAGE OPTIMIZATION
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
Voltage- and ABB-island optimization in high level synthesis
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.