Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Managing standby and active mode leakage power in deep sub-micron design
Proceedings of the 2004 international symposium on Low power electronics and design
Nanoscale CMOS circuit leakage power reduction by double-gate device
Proceedings of the 2004 international symposium on Low power electronics and design
Challenges and design choices in nanoscale CMOS
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the lowpower and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 µm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.