Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Silicon CMOS devices beyond scaling
IBM Journal of Research and Development - Advanced silicon technology
IBM Journal of Research and Development - Advanced silicon technology
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
The potential of Fe-FET for robust design under variations: A compact modeling study
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Subthreshold circuit design is a strong candidate for use in future low power applications. It is not clear, however, that device scaling to 45nm and beyond will be beneficial in Subthreshold circuits. We investigate the implications of device scaling on subthreshold circuits and find that the slow scaling of gate oxide thickness leads to a 60% reduction in Ion/Ioff between the 90nm and 32nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-Vth circuits.