IBM Journal of Research and Development - Advanced silicon technology
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
Product-representative "At speed" test structures for CMOS characterization
IBM Journal of Research and Development - Advanced silicon technology
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Microelectronic Engineering
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
Why should we do 3D integration?
Proceedings of the 45th annual Design Automation Conference
Study of leakage current mechanisms in ballistic deflection transistors
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimization and process variation analysis of nano-scale transistors
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Wafer-level 3D integration technology
IBM Journal of Research and Development
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
A Parallel Implementation of Electron-Phonon Scattering in Nanoelectronic Devices up to 95k Cores
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Analyzing the Next Generation Software Defined Radio for Future Architectures
Journal of Signal Processing Systems
Logic synthesis for integrated optics
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Circuit design challenges at the 14nm technology node
Proceedings of the 48th Design Automation Conference
Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
Software-defined massive multicore networking via freespace optical interconnect
Proceedings of the ACM International Conference on Computing Frontiers
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To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.