Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Silicon CMOS devices beyond scaling
IBM Journal of Research and Development - Advanced silicon technology
Optical Interconnect Opportunities for Future Server Memory Systems
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
VL2: a scalable and flexible data center network
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on Computer architecture
Helios: a hybrid electrical/optical switch architecture for modular data centers
Proceedings of the ACM SIGCOMM 2010 conference
IEEE Spectrum
Dark silicon and the end of multicore scaling
Proceedings of the 38th annual international symposium on Computer architecture
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
Proceedings of the 9th conference on Computing Frontiers
Tolerating process variations in nanophotonic on-chip networks
Proceedings of the 39th Annual International Symposium on Computer Architecture
A micro-architectural analysis of switched photonic multi-chip interconnects
Proceedings of the 39th Annual International Symposium on Computer Architecture
Proceedings of the 39th Annual International Symposium on Computer Architecture
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This paper presents a new frontier where future computer systems can continue to evolve as CMOS technology reaches its fundamental performance and density scaling limits. Our idea adopts freespace circuit-switched optical interconnect in massive multicore networking on chips and modules to flexibly configure private cache-coherent networks for allocated groups of cores in a software-defined manner. The proposed scheme can avoid networking inefficiencies due to the core resource fragmentation by providing deterministically lower latencies and higher bandwidth while advancing the technology roadmap with lower power consumption and improved cooling. We also discuss implementation plan and challenges for our proposal.