Recent developments in deca-nanometer vertical MOSFETs
Microelectronic Engineering - Special issue: Proceedings of the 13th biennial conference on insulating films on semiconductors
Silicon CMOS devices beyond scaling
IBM Journal of Research and Development - Advanced silicon technology
Reducing parasitic BJT effects in partially depleted SOI digital logic circuits
Microelectronics Journal
CMOS scaling beyond 32nm: challenges and opportunities
Proceedings of the 46th Annual Design Automation Conference
The ending of optical lithography and the prospects of its successors
Microelectronic Engineering
A physically based mobility model for numerical simulation of nonplanar devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness t"s"i were evaluated for 20-100nm channel length. The source region was found to merge at pillar thickness below 75nm, which results in floating body effect and creates isolated region in the middle of pillar. The vertical devices using ORI method show better performance than those with conventional implantation method for all pillar thickness, due to the elimination of corner effect that degrades the gate control. The presence of isolated depletion region in the middle of pillar at floating body increases parasitic effect for higher drain potential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device.