SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Circuit styles and strategies for CMOS VLSI design on SOI
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
SOI circuit design concepts
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
SOI technology for the GHz era
IBM Journal of Research and Development
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This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.