SOI digital CMOS VLSI—a design perspective

Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology

Proceedings of the 37th Annual Design Automation Conference

Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Proceedings of the 38th annual Design Automation Conference

Synthesis of low-leakage PD-SOI circuits with body-biasing

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

CAD Issues for CMOS VLSI Design in SOI

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

SOI Transistor Model for Fast Transient Simulation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Design and CAD Challenges in sub-90nm CMOS Technologies

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

Microelectronics Journal

The circuit and physical design of the POWER4 microprocessor

IBM Journal of Research and Development

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems