Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CAD Issues for CMOS VLSI Design in SOI
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
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In this paper, we extend transistor-level static noise analysis tools to consider the unique features of partially-depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body-potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable, regular switching activity. Results are presented using a commericial static noise analysis tool incorporating these extensions.