CAD Issues for CMOS VLSI Design in SOI

Authors:
Affiliations:
Venue:
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Year:
2001

Citing 5
Cited 1

Noise in deep submicron digital design

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SOI digital CMOS VLSI—a design perspective

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology

Proceedings of the 37th Annual Design Automation Conference
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Harmony: static noise analysis of deep submicron digital integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Statistical timing and leakage power analysis of PD-SOI digital circuits

Analog Integrated Circuits and Signal Processing

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Abstract

This paper reviews recent progress in making circuit-level CAD tools for the design of digital integrated circuits SOI-aware, specifically transistor-level static timing and static noise analysis tools. This involves abstracting the SOI device physics of the floating body, allowing estimates of the body voltage variation under various switching activity assumptions. These body voltage estimates are then applied as "initial conditions" in the constituent simulations of the static analyses. Results are presented for a prototype static timing analysis tool and a commercial static noise analysis tool.