Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
CAD Issues for CMOS VLSI Design in SOI
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient techniques for gate leakage estimation
Proceedings of the 2003 international symposium on Low power electronics and design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Leakage Current Modeling in PD SOI Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Probability and Random Processes For EE's (3rd Edition)
Probability and Random Processes For EE's (3rd Edition)
SOI technology for the GHz era
IBM Journal of Research and Development
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.