Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing and leakage power analysis of PD-SOI digital circuits
Analog Integrated Circuits and Signal Processing
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In this paper we demonstrate the transient behavior of off-state device leakage due to signal switching history in PD SOI devices. We address the leakage modeling for PD SOI circuits taking input switching history into account and demonstrate that the off-state power dissipation is a function of the device input duty cycle due to body voltage variations with switching history in SOI devices. We also demonstrate that the device off-state power dissipation can be 2.4 times higher than the power dissipation calculated with traditional steady state off-state device current.