Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Operator-based model-order reduction of linear periodically time-varying systems
Proceedings of the 42nd annual Design Automation Conference
Current source modeling for power and timing analysis at different supply voltages
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Noise analysis and power distribution network reliability assessment is extremely important in deep sub-micron digital and mixed-signal circuit design. Both relate closely to the nonlinear loading impact of digital circuits. Consequently, accurate estimation of the latter is critical. In this paper, we present extraction techniques that automatically generate a family of small, time-varying macromodels for digital cell libraries, at the time of their library characterization. Our approach is based on importing and adapting the Time-Varying Padé (TVP) method, for linear time-varying (LTV) model reduction, from the mixed-signal macromodelling domain. Our approach features naturally higher accuracy than previous ones, and in addition, offers the user a tradeoff between accuracy and macromodel complexity. A key attraction of our approach is that it can be merged into cell library extraction methodologies to produce accurate-by-construction noise models for digital blocks. Simulations and comparisons confirming the efficacy of our approach are provided.