di/dt Noise in CMOS Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Proceedings of the conference on Design, automation and test in Europe
On the interaction of power distribution network with substrate
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
4G terminals: how are we going to design them?
Proceedings of the 40th annual Design Automation Conference
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 41st annual Design Automation Conference
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analyzing software influences on substrate noise: an ADC perspective
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Properties of digital switching currents in fully CMOS combinational logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.