High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
A scalable substrate noise coupling model for mixed-signal ICs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Modeling of Substrate Noise Injected by Digital Libraries
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Principles of substrate crosstalk generation in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology
Analog Integrated Circuits and Signal Processing
SWAN: high-level simulation methodology for digital substrate noise generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Substrate noise (SN) is an important problem in mixed-signal designs. With increasing design complexity, it is not possible to simulate for SN with a detailed SPICE model that uses an accurate model for each transistor. In this paper, we propose a sensitivity analysis- and static timing analysis-based methodology to derive a reduced model that computes the worst case substrate noise in the design. The reduced model contains only passive components, which are very few, and is very quick to simulate. The main feature of our methodology is that, unlike previous approaches, it is independent of input patterns and does not need to simulate for millions of clock cycles. This lets us apply it to a full-chip design in reasonable CPU time. We validate our reduced model on several benchmark circuits against a detailed and highly accurate reference model. On average, the reduced model is within 16.4% of the reference model and is up to 38 times faster. Finally, we apply our methodology to a mixed-signal switch chip design consisting of 8 million gates and show that it finishes in 17 minutes.