DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Integrated circuit substrate coupling models based on Voronoi tessellation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. Once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated for a 2&mgr;m and a 0.5&mgr;m CMOS process where it is shown that the simple model predicts the noise coupling accurately. Measurements from a chip fabricated in a 0.5&mgr;m CMOS process show good agreement with the model.