Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Standard cell placement for even on-chip thermal distribution
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A scalable substrate noise coupling model for mixed-signal ICs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design
Analog Integrated Circuits and Signal Processing - Analog circuit techniques and related topics
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Substrate coupling in digital circuits in mixed-signal smart-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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We present a modeling technique for assessing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Since the magnitude of the noise problem is a function of the relative proximity of noisy and sensitive devices, design aids are required which can incorporate the switching noise effects at the post-layout phase of design verification. In our approach, SPICE-compatible lumped element RC substrate macromodels are efficiently generated from the circuit layout using a geometric construct called the Voronoi tessellation. The new models retain the accuracy of previously reported models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing larger circuits. The node count reduction is realized by deriving a model topology which automatically adapts itself to the local densities of substrate features associated with the noise coupling. Our strategy has been verified using detailed 2-D device simulation, and successfully applied to some mixed-A/D circuit examples