Computational geometry: an introduction
Computational geometry: an introduction
Extraction of circuit models for substrate cross-talk
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Integrated circuit substrate coupling models based on Voronoi tessellation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In integrated mixed-signal circuits signal integrity is affected by parasitic substrate coupling. Therefore, substrate crosstalk analysis has to be performed in layout verification. The PARasitic COUpling Model GeneratoR for Substrate (PARCOURS) applies a three-dimensional model for the substrate considering conductivity and permittivity if required. As a remarkable feature PARCOURS uses different levels of accuracy. The highest level integrates circuit elements with multiple substrate terminals in order to model the flow of parasitic currents in the vicinity of the die surface. The lowest level simplifies the substrate terminal as a point connection. A commercial videochip has been examined with the introduced approach.