Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Fast methods for extraction and sparsification of substrate coupling
Proceedings of the 37th Annual Design Automation Conference
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's
Proceedings of the conference on Design, automation and test in Europe
A benchmark suite for substrate analysis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
On the interaction of power distribution network with substrate
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Combined BEM/FEM substrate resistance modeling
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simulation approaches for strongly coupled interconnect systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Characterizing Substrate Coupling in Deep-Submicron Designs
IEEE Design & Test
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast Computation of Substrate Resistances in Large Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An improved direct boundary element method for substrate coupling resistance extraction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Substrate resistance extraction with direct boundary element method
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Substrate model extraction using finite differences and parallel multigrid
Integration, the VLSI Journal
Modeling and simulation of substrate noise in mixed-signal circuits applied to a special VCO
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper proposes a Boundary Element Method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.In contrast with standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.