Fast Computation of Substrate Resistances in Large Circuits

Authors:
A. J. Van Genderen;N. P. van der Meijs;T. Smedes
Affiliations:
Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands;Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands;Philips Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 5
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Abstract

In this paper, we describe a method to quickly and accurately estimate substrate coupling effects in analog and mixed digital/analog integrated circuits. Unlike numerical methods, that can be used for circuits containing only a few hundreds of substrate terminals, the new method can quickly extract circuits containing many thousands of substrate terminals. Examples are given that show that the method is sufficiently accurate for practical circuit verification. The method has been implemented in the layout-to-circuit extractor Space.