Efficient parasitic substrate modeling for monolithic mixed-A/D circuit design and verification
Analog Integrated Circuits and Signal Processing - Special issue: modeling and simulation of mixed analog-digital systems
Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits
Analog Integrated Circuits and Signal Processing
Fast Computation of Substrate Resistances in Large Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Integrated circuit substrate coupling models based on Voronoi tessellation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and application of adaptive delay sequential elements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.