The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Substrate coupling in digital circuits in mixed-signal smart-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing Analysis in Presence of Power Supply and Ground Voltage Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Layout driven synthesis of multiple scan chains
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Lower operating voltages and faster clock frequencies in advanced fabrication processes increase the circuit delay sensitivity to voltage, temperature, and process variations and modeling approximations. Uncorrelated delay variations along data and clock paths cause timing violations. In this paper, we propose a method for correcting timing violations by in-circuit tuning of clock latencies after fabrication. We introduce adaptive delay sequential elements (ADSEs) that use charge storage on pMOS floating gates to tune the clock latencies of timing critical flip-flops. ADSEs facilitate in-circuit optimization of clock latencies under varying operating conditions. ADSE tuned clock latencies are nonvolatile and can be repeatedly adjusted after fabrication using only electrical signals. We present examples of implicit and explicit pulsed ADSEs and their tuning operations. Our experiments with fabricated prototypes show that ADSEs can tune their clock latencies with picosecond resolution over one-half of the clock period. Our experiments also show that ADSE sensitivities to supply voltage, temperature, noise, and transistor mismatch are comparable to nonadaptive sequential elements. We present experimental data that show ADSE tuned delays change only 15% after ten years at 125°C. We propose a method for selective tuning of embedded ADSEs and demonstrate its application in a fabricated prototype. ADSEs can selectively replace timing-critical flip-flops of a circuit with negligible area impact.