Latchup in CMOS technology: the problem and its cure
Latchup in CMOS technology: the problem and its cure
Extraction of circuit models for substrate cross-talk
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Noise considerations for mixed-signal RF IC transceivers
Wireless Networks - Special issue VLSI in wireless networks
Combined BEM/FEM substrate resistance modeling
Proceedings of the 39th annual Design Automation Conference
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Accurate Substrate Noise Analysis Based on Library Module Characterization
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
SWAN: high-level simulation methodology for digital substrate noise generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Substrate Noise Coupling in Mixed-Signal ASICs
Substrate Noise Coupling in Mixed-Signal ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Principles of substrate crosstalk generation in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.