Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
Fast methods for extraction and sparsification of substrate coupling
Proceedings of the 37th Annual Design Automation Conference
Modeling and simulation of the interference due to digital switching in mixed-signal ICs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC
Proceedings of the 39th annual Design Automation Conference
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation approaches for strongly coupled interconnect systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling digital substrate noise injection in mixed-signal IC's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bibliography on cyclostationarity
Signal Processing
Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identification of dominant noise source and parameter sensitivity for substrate coupling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a suite of commercial tools in combination with a high-speed extractor based on an innovative semi-analytical method to deal with noise coupling problems, and enable RF designers to achieve a first silicon-success of their chips. The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver demonstrated.