High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
Probability and statistics with reliability, queuing and computer science applications
Probability and statistics with reliability, queuing and computer science applications
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Modeling of Substrate Noise Injected by Digital Libraries
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Substrate Coupling: Modeling, Simulation and Design Perspectives
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Substrate optimization based on semi-analytical techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.