Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Low Power Digital CMOS Design
Noise Reduction Using Low Weight and Constant Weight Coding Techniques
Noise Reduction Using Low Weight and Constant Weight Coding Techniques
High-level simulation of substrate noise generation including power supply noise coupling
Proceedings of the 37th Annual Design Automation Conference
Scaling trends of on-chip Power distribution noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robustness of radial basis functions
Neurocomputing
Worst case power/ground noise estimation using an equivalent transition time for resonance
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Distributed power network co-design with on-chip power supplies and decoupling capacitors
Proceedings of the System Level Interconnect Prediction Workshop
Simultaneous switching noise reduction by resonant clock distribution networks
Integration, the VLSI Journal
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This is an overview paper presenting di/dtnoise from a designer‘s perspective. Analysis and circuit designtechniques are presented taking package parasitics into account.The main focus is on digital CMOS design, but analysis and designsuggestions can easily be extended to mixed-mode design.