di/dt Noise in CMOS Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Power distribution in high-performance design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Properties of on-chip inductive current loops
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Impedance characteristics of power distribution grids in nanoscale integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Gate delay estimation in STA under dynamic power supply noise
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient distributed on-chip decoupling capacitors for nanoscale ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analog Integrated Circuits and Signal Processing
Integration, the VLSI Journal
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The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S 1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S2 in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates he scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.