Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
High-level current macro-model for power-grid analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
An electromigration and thermal model of power wires for a priori high-level reliability prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous power supply planning and noise avoidance in floorplan design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UDSM trends comparison: from technology roadmap to UltraSparc Niagara2
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, a priori dynamic voltage drop evaluation is the focus of this work. It takes into account transient currents and on-chip and package RLC parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable results.