A dynamic jitter model to evaluate uncertainty trends with technology scaling

Authors:
Mónica Figueiredo;Rui L. Aguiar
Affiliations:
Department of Electrical Engineering, Escola Superior de Tecnologia e Gestão, Instituto Politécnico de Leiria, 2411-901 Leiria, Portugal and Institute of Telecommunications, Pólo de ...;Department of Electronics, Telecommunications and Informatics, Universidade de Aveiro, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal and Institute of Telecommunications, Pó ...
Venue:
Integration, the VLSI Journal
Year:
2012

Citing 13
Cited 0

Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections

Integration, the VLSI Journal
Miller factor for gate-level coupling delay calculation

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Conquering Noise in Deep-Submicron Digital ICs

IEEE Design & Test
Buffer delay change in the presence of power and ground noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Scaling trends of on-chip power distribution noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Jitter Models and Measurement Methods for High-Speed Serial Interconnects

ITC '04 Proceedings of the International Test Conference on International Test Conference
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis

VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations

Integration, the VLSI Journal
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electrical and optical clock distribution networks for gigascale microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic crosstalk delay estimation for ASICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.01

Visualization

Abstract

Clock jitter can no longer be considered negligible when compared to clock skew. Its unpredictability and high-frequency content makes it an increasingly limiting factor to performance in modern digital systems. In this paper, we investigate dynamic jitter and uncertainty trends, as technology continues scaling to the nanometric region. Simulation results are used to derive heuristic metrics for the sensitivity of a generic repeater to dynamic variability sources. These metrics are then used to discuss clock precision degradation with technology scaling. Using parameters that can be easily obtained, the proposed model can be useful to assess the expected behavior of existing and future technologies in terms of clock precision. Also, it provides a valuable insight regarding the key circuit parameters responsible for dynamic jitter insertion.