Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal resilient bounded-skew clock tree optimization methodology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
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Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non-negligible impact on delay and reliability is getting significant attention lately. One of the principal factors affecting designs today is timing criticality, which, in today's technologies is mostly determined by wire delays. Clocks, which are the backbone of the interconnect network, are extremely prone to temperature dependent delay variations and need to be designed with extreme care so as to meet accurate timing constraints. Their skew has to be minimized in order to guarantee functionality, albeit in the presence of these process variations. Temperature, on the other hand, is dynamic in nature and its effects hence need run-time monitoring and management. One of the most efficient ways to manage temperature dependent skew is through the use of buffers with dynamically tunable delays. The use of such buffers in the clock distribution network allows modulating the delay on selected branches of the clock network based on a thermal profile, so as to keep the skew within acceptable bounds. A runtime scheme obviously requires an on-line management unit. Our work predominantly focuses on the implementation of one such unit, while studying its impact on design parameters such as area, wire-length and power. Results show negligible a impact (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number) on the design.