Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect and noise immunity design for the Pentium 4 processor
Proceedings of the 40th annual Design Automation Conference
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A practical methodology for early buffer and wire resource allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimum positioning of interleaved repeaters in bidirectional buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal derivation of optimal active shielding for low-power on-chip buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting parity computation latency for on-chip crosstalk reduction
IEEE Transactions on Circuits and Systems II: Express Briefs
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires
Microelectronics Journal
| Hi-index | 0.00 |
Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.