Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Formal derivation of optimal active shielding for low-power on-chip buses
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
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Reduction of worst-case delay and delay uncertainty due to capacitivecoupling is a still unsolved problem in physical design.We describe a routing only layout solution - swizzling - whichreduces worst-case coupling delay for long parallel wires suchas in wide on-chip global buses. We understand that swizzlingis a folklore in structured-custom design community but we arethe first to describe the method and analyze the potential benefitsin literature. We give a general method for construction of goodswizzling patterns. We also give empirically determined, optimalswizzling patterns for various technology nodes and typicalrepeater intervals. From our results, we see up to 31.5%reduction in worst-case delay and 34% reduction in delay uncertainty.