Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses
Proceedings of the 2004 international symposium on Low power electronics and design
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
IEEE Computer Architecture Letters
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using well-solvable quadratic assignment problems for VLSI interconnect applications
Discrete Applied Mathematics
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A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally shared. The existence of a unique power-optimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed prior to spacing optimization. By using this order of wires, optimality of the combined solution is guaranteed (as compared with any other ordering and spacing of the wires). Timing-aware power optimization is enabled by simultaneously considering timing criticality weights and activity factors for the signals. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from high-end microprocessor circuits in 65 nm technology. Interconnect power reduction of 17% on average has been observed in such bundles.