An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
Proceedings of the 50th Annual Design Automation Conference
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Modeling sleep mode gains in energy-aware networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
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Power consumption is a key issue in highperformanceinterconnection network design. Communicationlinks, already a aignificant consumer of power now,will take up an ever larger portion of the power budgetas demand for network bandwidth increases. In this paper,we motivate the use of dynamic voltage scaling (DVS)for links, where the frequency and voltage of links are dynamicallyadjusted to minimize power consumption. Wepropose a history-based DYS algorithm that jjlidiciously adjustsDVS poIicies based on past link utilization. Despitevery conservative assumptions about DVS link characteristics,our approach realizes up to 4.5X power savings (3.2Xaverage), with just an average 27.4% Iatency increase and2.5% throughput reduction. To the best of our knowledge,this is the first study that targets dynamic power optimizationof interconnection networks.