Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Throughput-centric routing algorithm design
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
IEEE Computer Architecture Letters
Globally Adaptive Load-Balanced Routing on Tori
IEEE Computer Architecture Letters
Adaptive Power Management for the On-Chip Communication Network
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
Proceedings of the 45th annual Design Automation Conference
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Multiple clock and voltage domains for chip multi processors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Energy proportional datacenter networks
Proceedings of the 37th annual international symposium on Computer architecture
Supervised learning based power management for multicore processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
NoC frequency scaling with flexible-pipeline routers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
NOCS '12 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
ORION 2.0: A Power-Area Simulator for Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In chip design today and for a foreseeable future, the last-level cache and on-chip interconnect is not only performance critical but also a substantial power consumer. This work focuses on employing dynamic voltage and frequency scaling (DVFS) policies for networks-on-chip (NoC) and shared, distributed last-level caches (LLC). In particular, we consider a practical system architecture where the distributed LLC and the NoC share a voltage/frequency domain that is separate from the core domain. This architecture enables the control of the relative speed between the cores and memory hierarchy without introducing synchronization delays within the NoC. DVFS for this architecture is more complex than individual link/core-based DVFS since it involves spatially distributed monitoring and control. We propose an average memory access time (AMAT)-based monitoring technique and integrate it with DVFS based on PID control theory. Simulations on PARSEC benchmarks yield a 27% energy savings with a negligible impact on system performance.